2012 IEEE 55th International Midwest Symposium on Circuits and SystemsFifth International Workshop on System-on-Chip for Real-Time Applications, 2005

Harmanani, HaidarHarmanani, H.; Karablieh, B.

Fifth International Workshop on System-on-Chip for Real-Time Applications, 2005

Title: Fifth International Workshop on System-on-Chip for Real-Time Applications, 2005;
A hybrid distributed test generation method using deterministic and genetic algorithms

Harmanani, H.; Karablieh, B.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University

URI: http://hdl.handle.net/10725/5460

URL: http://ieeexplore.ieee.org/abstract/document/1530964/

DOI: http://dx.doi.org/10.1109/IWSOC.2005.13

Abstract:

Test generation is a highly complex and time-consuming task. In this work, we present a distributed method for combinational test generation. The method is based on a hybrid approach that combines both deterministic and genetic approaches. The deterministic phase is based on the D-algorithm and generates an initial set of test vectors that are evolved in the genetic phase in order to achieve high fault coverage in a short time. The algorithm is parallelized based on a cluster of workstations using the message passing interface (MPI) library. Several benchmark circuits were attempted, and favorable results comparisons are reported

Citation:

Harmanani, H., & Karablieh, B. (2005, July). A hybrid distributed test generation method using deterministic and genetic algorithms. In System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on (pp. 317-322). IEEE.