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SoAS - Scholarly Publications: Recent submissions

  • Canadian Conference on Electrical and Computer Engineering, 2001 
    Harmanani, H.; Saliba, R.; Khoury, M.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    A high level synthesis for testability method is presented with the objective to generate testable resistor transistor logic designs from behavioral descriptions. The approach is formulated as an allocation problem and ...
  • The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004 
    Harmanani, H.; Marrouche, W.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    This work presents a method for distributed test control in coordination with testable data path allocation in high-level synthesis. The method aims at creating distributed test controllers for synthesized data paths with ...
  • Fifth International Workshop on System-on-Chip for Real-Time Applications, 2005 
    Harmanani, H.; Karablieh, B.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Test generation is a highly complex and time-consuming task. In this work, we present a distributed method for combinational test generation. The method is based on a hybrid approach that combines both deterministic and ...
  • 2006 IEEE North-East Workshop on Circuits and Systems 
    Harmanani, Haidar M.; Salamy, Hassan A.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of ...
  • 50th Midwest Symposium on Circuits and Systems, 2007 
    Harmanani, Haidar M.; Farah, Rana; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    System-on-chip (SOCs) test minimization has received a lot of attention in the past few years. However, most recent work assumed flat hierarchy. This assumption is unrealistic especially in the case of non-mergeable legacy ...
  • IEEE Northeast Workshop on Circuits and Systems, 2007 
    Harmanani, Haidar M.; Sawan, Rachel; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Test access is a major problem in testing embedded cores as it directly impacts testing time and hardware cost. Test access mechanism (TAM) is responsible for test data transport and is characterized by its bandwidth ...
  • Canadian Conference on Electrical and Computer Engineering, 2007 
    Harmanani, Haidar M.; Sawan, Rachel; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Test access mechanism (TAM) is an important element of test access architectures for embedded cores and is responsible for on-chip test patterns transport from the source to the core under test to the sink. Efficient TAM ...
  • Canadian Conference on Electrical and Computer Engineering, 2008 
    Harmanani, Haidar M.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuos increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for ...
  • 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference 
    Harmanani, Haidar M.; Farah, Rana; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a ...
  • 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference 
    Harmanani, Haidar M.; Farah, Rana; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC test schedules with wrapper design and TAM optimization based ...
  • 2010 23rd Canadian Conference on Electrical and Computer Engineering 
    Harmanani, Haidar M.; Kodeih, Maya; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    This paper presents a method for concurrent BIST cost estimation during testable data path allocation. The method integrates testability in the design process and generates a distributed test controller that aims to minimize ...
  • 2010 IEEE International SOC Conference 
    Harmanani, Haidar; Farah, Rana; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a ...
  • 2011 IEEE International Conference on Information Reuse and Integration 
    Harmanani, Haidar; Azar, Danielle; SAS; 199490170; 198833240; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; danielle.azar@lau.edu.lb; Lebanese American University (IEEE, )
    Rule-based classifiers are supervised learning techniques that are extensively used in various domains. This type of classifiers is popular because of its nature which makes it modular and easy to interpret and also because ...
  • 2011 24th Canadian Conference on Electrical and Computer Engineering 
    Harmanani, Haidar M.; Salamy, Hassan; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    With the growing trend of increasing number of cores on a single chip, bus-based communication is suffering from bandwidth and scalability issues. As a result, the new approach is to use a network on chip (NoC) as the main ...
  • 2012 IEEE 55th International Midwest Symposium on Circuits and Systems 
    Harmanani, Haidar; Salamy, Hassan; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    As more cores are being packed on a single chip, bus-based communication is suffering from bandwidth and scalability issues. As a result, the new approach is to use a network-on-chip (NoC) as the main communication platform ...
  • 29th International Conference on Computers and Their Applications 
    Harmanani, Haidar; Helal, Nathalie; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University
    The Split Delivery Vehicle Routing Problem with Time Windows (SDVRPTW) is a variation of the vehicle routing problem (VRP) that incorporates time windows and split delivery constraints. The VRP is a generalization of ...
  • 2014 21st IEEE International Conference on Electronics, Circuits and Systems 
    Harmanani, Haidar M.; Ferzli, Rony; Anabtawi, Nijad; SAS; 199490170; Computer Science and Mathematics; Lebanese American University (IEEE, )
    A well-known limitation of sigma delta modulators is the generation of limit cycle oscillations for DC and slow varying inputs. These limit cycles give rise to undesired tones at the output of the modulator which result ...
  • 2016 IEEE International Symposium on Circuits and Systems 
    Harmanani, Haidar M.; Ferzli, Rony; Anabtawi, Nijad; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    This paper presents a step down, switched mode power converter for use in multi-standard envelope tracking radio frequency power amplifiers (RFPA). The converter is based on a programmable order sigma delta modulator that ...
  • The 2nd Annual IEEE Northeast Workshop on Circuits and Systems 
    Harmanani, H.; Hajar, A.; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, ...
  • 2016 IEEE International Symposium on Circuits and Systems 
    Harmanani, Haidar M.; Ferzli, Rony; Anabtawi, Nijad; SAS; 199490170; Computer Science and Mathematics; haidar.harmanani@lau.edu.lb; Lebanese American University (IEEE, )
    This paper presents a switching DC-DC Buck converter with enhanced light-load efficiency for use in noise-sensitive applications. Low noise, spur free operation is achieved by using a sigma-delta-modulator (ΣΔ) based ...

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